Figure below shows the maximum length sequence produced by a 4 bit LFSR. The one shown above is an 8-taps LFSR (it uses 8 flip-flops). For a small LFSR like the present one (4bit) its easy to identify the Taps to the XOR gate which can produce maximum length output but just imagine how can we identify the Taps for the XOR if the number of bits is 10bits ? Obviously we cant go by BRUTE FORCE method by trying all possible combination to identify the Taps which will produce maximum length sequence. As you can see, an LFSR is a shift-register with some XOR gates. In our example if the LFSR has to be of maximum length then the pattern has to repeat after 16(2^4) clock cycles. By maximum length we mean that the pattern must repeat itself after 2^N clock cycles for a N bit LFSR. This is obviously a very trivial form of encryption that's not very secure, but it's cheap-and-cheerful and may be useful in certain applications. But the pattern has to be of maximum length . The stream of encrypted data bits seen by a receiver can be decrypted by XOR-ing them with the output of an identical LFSR. There is no such order from where the inputs to the XOR comes from to produce a random pattern. So from the figure above the Taps are 0 and 3 FF's. The inputs to the XOR are called the Taps. This is a general structure for a 4 bit LFSR. When we take out the output of these FF they will have a random pattern. Just wait for a few clock impulses and watch the output values of the register, which should appear more or less random. In this example, the outputs of flipflops 8,6,5,4 are summed via XNOR gates (this is a linear operation, hence the name) and fed back into the first flipflop. This XOR operation introduces a new bit into the shift register. A simple 8-bit linear feedback shift register built from D-flipflops.

But the only change is that the input to the first (D3 in th figure) is from the XOR of the o/p from FF's 0 and 3 (from fig). It consist of D-FF connected in cascade as shown with the same clock applied to all the FF to make them act like a shift register.

Linear feedback shift register verilog